TBUAAVFQ1N10D

TBUAAVFQ1N10D

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LCD&VGA控制器设计
    
设计行场扫描时序，一般有两种方式：查找表方式和编程逻辑方式。查找表方式主要由存储芯片构成，如SRAM、EPROM、PORM等。使用时，先根据所要产生的时序在存储单元写进相应的数值，查表时再从表内读出时应存储单元的数值，以形成扫描时序。扫描时序查找表分为行扫描时序查找表和场扫描时序查找表。场扫描时序查找表的输进时钟由行同步脉冲提供。用查找表形成时序的方法存在体积大、计算烦琐的缺点。随着大规模逻辑芯片的出现，利用编程逻辑方法产生行场扫描时序是一个发展方向。这种方法具有电路简单、功能强、修改方便、可靠性高等优点。图3为LCD控制器的框图。
    
在本设计中，点时钟DCLK由处理器DSP的系统时钟40MHz经数字锁相环二分频得到。点时钟驱动行时序天生器，产生图2所示的行同步信号HS和行消隐信号HB。为避免毛刺，控制器设计采用同步设计方法，如图3所示，行同步信号HS通过一个微分电路，产生一个点时钟周期宽的场时序天生器使能信号。在使能信号有效时，场时序天生器开始计数，并产生场同步信号VS和场消隐信号VB。行消隐信号HB和场消隐信号VB相与后即为数据使能信号DATA_EN。该数据使能信号作为产生帧存地址计数器的计数使能，以保证DATA_EN信号为高时，将象素送给AMLCD显示。在DCLK的上升沿，帧存地址计数器加一，帧存SRAM经过一段延时后，象素数据出现在总线上。在DCLK的下降沿AMLCD将数据读进。该LCD控制器的设计方法很轻易用于VGA视频接口。在VGA接口电路的设计中，不需点时钟电路，只须将行同步信号与场同步信号输出，将数据使能信号作为复合消隐信号输进即可。产生行场扫描时序的VHDL描述如下：
entityseq_genis
port(clk_seq:instd_logic；
rst_seq:instd_logic;
lcd_hs_out:outstd_logic;
lcd_dataen:outstd_logic;
lcd_vs_out:outstd_logic;
pix_clk:outstd_logic);
endseq_gen;
architecturertl_seq_genofseq_genis
signallcd_hb:std_logic;
signallcd_hs:std_logic;
signallcd_vb:std_logic;
signallcd_vs:std_logic;
signalclken_vcount:std_logic;
begin
hcount:block
signalhcountreg:std_logic_vector(9downto0);
signalhz_temp:std_logic;
signallcd_hz:std_logic;
begin
process(clk_seq,lcd_hz)
begin
if(lcd_hz='1')then
hcountreg<=(others=>'0');
elsifclk_seq'eventandclk_seq='1'then
hcountreg<=hcountreg+1;
endif;
endprocess;sp; lcd_hb<='0'whenhcountreg>=600andhcountreg<650
else'1';
lcd_hs<='0'whenhcountreg>=610andhcountreg<630
else'1';
hz_temp<='1'whenhcountreg=650else'0';
lcd_hz<=hz_temporrst_seq;
endblockhcount;
diff:block
signalinputrega:std_logic;
signalinputregb:std_logic;
begin
process(clk_seq)
begin
ifclk_seq'eventandclk_seq='1'then
inputregb<=inputrega;
inputrega<=notlcd_hs;
endif;
endprocess;
clken_vcount<=notinputregbandinputrega;
endblockdiff;
vcount:block
signalvcountreg:std_logic_vector(9downto0);
signalvz_temp:std_logic;
signallcd_vz:std_logic;
begin
process(clk_seq,lcd_vz)
begin
if(lcd_vz='1')then
vcountreg<=(others=>'0');
elsifclk_seq'eventandclk_seq='1'then
ifclken_vcount='1'then
vcountreg<=vcountreg+1;
endif;
endif;
endprocess;
lcd_vb<='0'whenvcountreg>=600andvcountreg<615
else'1';
lcd_vs<='0'whenvcountreg>=607andvcounreg<610
else'1';
vz_temp<='1'whenvcountreg=615else'0';
lcd_vz<=vz_temporrst_seq;
endblockvcount;
pix_clk<=clk_seq;
lcd_dataen<=lcd_hbandlcd_vb;
lcd_hs_out<=lcd_hs;
lcd_vs_out<=lcd_vs;
endrtl_seq_gen;
    
这种用VHDL产生扫描时序的方法简单、易读，并且易于修改。在代码中只须修改一些时序参数就能产生任意时序的波形，具有很好的可重用性。用FPGAExpress3.5半VHDL代码综合后，通过Foundation3.1i进行布局和布线，用Foundation提供的门级仿真工具产生的行扫描时序仿真图。
    
采用FPGA技术设计的AMLCD控制器，大大减少了电路板的尺寸，同时增加了系统可靠性和设计灵活性。这种用VHDL语言实现现行场扫描时序天生器的方法，具有简便。易读和可重用性强的特点。该AMLCD控制器已用Xilinx公司的SpartanII系列器件XC2S50实现，并在飞机座舱图形显示系统中实现应用。
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